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asahi kasei [ak4126] ms0544-e-00 2006/09 - 1 - general description ak4126 is a 6ch digital sample rate converter (src). the input sample rate ranges from 8khz to 192khz. the output sample rate is from 8khz to 192khz. by using the ak4126, the system can take very simple configuration because the ak4126 has an internal pll and does not need any master clock then the ak4126 is suitable for the application interfacing to different sample rates like multi-channel high-end car audio, dvd recorder, etc. features 1. src ? 6 channels input/output ? asynchronous sample rate converter ? input sample rate range (fsi): 8khz 192khz ? output sample rate range (fso): 8khz 192khz ? input to output sample rate ratio: 1/6 to 6 ? thd+n: ? 130db ? dynamic range: 140db (a-weighted) ? i/f format: msb justified, lsb justified and i 2 s compatible ? pll for internal operation clock ? digital de-emphasis filter (32khz, 44.1khz and 48khz) ? soft mute function 2. power supply ? avdd, dvdd: 3.0 3.6v (typ. 3.3v) 3. ta = ? 40 85 c 4. package: 64lqfp 6ch 192khz / 24-bit asynchronous src ak4126
asahi kasei [ak4126] ms0544-e-00 2006/09 - 2 - pll pdn smute olrck obick sdto1 serial audio i/f src serial audio i/f ilrck sdti1 ibick pll1 pll2 idif2 idif1 idif0 odif1 odif0 obit1 obit0 unlock dvdd dvss pll0 dither sdti2 sdti3 sdto2 sdto3 dem pm smt1 smt0 dem1 dem0 avdd avss figure 1. ak4126 block diagram ? compatibility with ak4125 parameter ak4126 ak4125 channel 6ch 2ch maximum sampling frequency 192khz 216khz maximum bick frequency 64fs 128fs bypass mode no yes master mode no yes de-emphasis yes no variable soft mute cycle yes no group delay typ. 57/fs typ. 56/fs package 64lqfp(12mm x 12mm) 30vsop (9.7mm x 7.6mm)
asahi kasei [ak4126] ms0544-e-00 2006/09 - 3 - ? application block circuit example 1. most ? amp unit most a k4126 bick lrck sdto ibclk ilrck sdti1-3 obclk olrck sdto1-3 a sic bclk lrck sdti 3 3 src fs = 192khz fs = 176.4khz fs = 96khz fs = 88.2khz fs = 48khz fs = 44.1khz fs = 96khz fs = 88.2khz fs = 48khz fs = 44.1khz src 2. dvd (5.1ch) ? most or asic a sic (endec) a k4126 bick lrck sdto ibclk ilrck sdti1-3 obclk olrck sdto1-3 most or asic bclk lrck sdti 3 3 src fs = 192khz fs = 96khz fs = 48khz fs = 96khz fs = 88.2khz fs = 48khz fs = 44.1khz src
asahi kasei [ak4126] ms0544-e-00 2006/09 - 4 - ? ordering guide AK4126VQ ? 40 +85 c 64lqfp (0.5mm pitch) akd4126 evaluation board for ak4126 ? pin layout nc nc 1 test0 64 2 ilrck 3 ibick 4 dvdd 5 dvss 6 tst0 7 sdti1 8 sdti2 9 sdti3 10 idif0 tst11 63 a vss 62 61 60 nc 59 tst10 58 tst9 57 pll0 56 pll1 55 pll2 54 tst5 17 tst3 18 tst4 19 unloc k 20 dvdd 21 22 smute 23 dither 24 pdn 25 smt0 26 smt1 27 48 47 46 45 44 43 42 41 40 39 38 nc test4 olrck obick dvdd dvss tst6 sdto1 sdto2 sdto3 odif0 top view dvss filt a vdd dvss 53 dem0 28 11 idif1 12 37 odif1 idif2 13 tst1 14 tst2 15 nc 16 dem1 29 pm 30 obit0 31 obit1 32 dvdd 52 tst8 51 tst7 50 nc 49 36 35 34 test3 test2 test1 33 nc
asahi kasei [ak4126] ms0544-e-00 2006/09 - 5 - pin / function no. pin name i/o function 1, 16, 33,48, 49,59, 64 nc - no connect pin. no internal bonding. this pin must be connected to dvss. 2 test0 i test pin this pin must be connected to dvss. 3 ilrck i input channel clock pin 4 ibick i audio serial data clock pin 5 dvdd - digital power supply pin, 3.0 3.6v 6 dvss - digital ground pin 7 tst0 i test pin this pin must be connected to dvss. 8 sdti1 i audio serial data input #1 pin 9 sdti2 i audio serial data input #2 pin 10 sdti3 i audio serial data input #3 pin 11 idif0 i audio interface format #0 pin for input port 12 idif1 i audio interface format #1 pin for input port 13 idif2 i audio interface format #2 pin for input port 14 tst1 i test pin this pin must be connected to dvss. 15 tst2 i test pin this pin must be connected to dvss. 17 tst3 i test pin this pin must be connected to dvss. 18 tst4 i test pin this pin must be connected to dvss. 19 unlock o unlock status pin 20 dvdd - digital power supply pin, 3.0 3.6v 21 dvss - digital ground pin 22 smute i soft mute pin ?h? : soft mute, ?l? : normal operation 23 dither i dither enable pin ?h? : dither on, ?l? : dither off 24 pdn i power-down mode pin ?h?: power up, ?l?: power down reset and initializes the control register. the ak4126 should be reset once by bringing pdn pin = ?l? upon power-up. 25 smt0 i soft mute timer select #0 pin 26 smt1 i soft mute timer select #1 pin 27 dem0 i de-emphasis control #0 pin 28 dem1 i de-emphasis control #1 pin 29 pm i 4ch/6ch mode select pin 30 obit0 i bit length select #0 pin for output data 31 obit1 i bit length select #1 pin for output data note: all input pins should not be left floating.
asahi kasei [ak4126] ms0544-e-00 2006/09 - 6 - pin / function no. pin name i/o function 32 tst5 i test pin this pin must be connected to dvss. 34 test1 i test pin this pin must be connected to dvdd. 35 test2 i test pin this pin must be connected to dvss. 36 test3 i test pin this pin must be connected to dvss. 37 odif1 i audio interface format #1 pin for output port 38 odif0 i audio interface format #0 pin for output port 39 sdto3 o audio serial data output #3 pin for output port 40 sdto2 o audio serial data output #2 pin for output port 41 sdto1 o audio serial data output #1 pin for output port 42 tst6 i test pin this pin must be connected to dvss. 43 dvss - digital ground pin 44 dvdd - digital power supply pin, 3.0 3.6v 45 obick i audio serial data clock pin for output port 46 olrck i output channel clock pin for output port 47 test4 i test pin this pin must be connected to dvss. 50 tst7 i test pin this pin must be connected to dvss. 51 tst8 i test pin this pin must be connected to dvss. 52 dvdd - digital power supply pin, 3.0 3.6v 53 dvss - digital ground pin 54 pll2 i pll mode select #2 pin 55 pll1 i pll mode select #1 pin 56 pll0 i pll mode select #0 pin 57 tst9 i test pin this pin must be connected to dvss. 58 tst10 i test pin this pin must be connected to dvss. 60 avdd - analog power supply pin, 3.0 3.6v 61 filt o pll loop filter pin 62 avss - analog ground pin 63 tst11 o test pin this pin must be open. note: all input pins should not be left floating.
asahi kasei [ak4126] ms0544-e-00 2006/09 - 7 - ? handling of unused pins the unused digital i/o pins should be processed appropriately as below. classification pin name setting smute, dither, pm, test0, test2 4, nc, tst0 10, sdti1, sdti2, sdti3 these pins must be connected to dvss. test1 this pin must be connected to dvdd. digital unlock, sdto1, sdto2, sdto3, tst11 these pins must be open. absolute maximum ratings (avss, dvss=0v; note 1) parameter symbol min max units power supplies: (note 2) analog digital avdd dvdd ? 0.3 ? 0.3 4.6 4.6 v v input current, any pin except supplies iin - 10 ma digital input voltage (note 3) vind ? 0.3 dvdd+0.3 v ambient temperature (power applied) (note 4) ta ? 40 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. avss and dvss must be connected to the same ground. note 3. idif2-0, dem1-0, odif1-0, obit1-0, olrck, obick, pdn, smute, pm, smt1-0, test4-0, tst10-0, pll2-0, sdti3-1, ilrck and ibick pins note 4. in case that wiring density is 100%. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 1) parameter symbol min typ max units power supplies: (note 5) analog digital avdd dvdd 3.0 3.0 3.3 3.3 3.6 3.6 v v difference avdd - dvdd -0.3 0 +0.3 v note 1. all voltages with respect to ground. note 5. the power up sequence between avdd and dvdd is not critical. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ak4126] ms0544-e-00 2006/09 - 8 - src characteristics (ta=25 c; avdd=dvdd=3.3v; avss=dvss=0v; signal frequency = 1khz; data = 24bit; measurement bandwidth = 20hz ~ fso/2; unless otherwise specified.) parameter symbol min typ max units src characteristics: resolution 24 bits input sample rate fsi 8 192 khz output sample rate fso 8 192 khz thd+n (input = 1khz, 0dbfs, note 6) fso/fsi = 44.1khz/48khz fso/fsi = 48khz/44.1khz fso/fsi = 48khz/192khz fso/fsi = 192khz/48khz worst case (fso/fsi = 32khz/176.4khz) - - - - - ? 130 ? 124 ? 133 ? 124 - - - - - ? 91 db db db db db dynamic range (input = 1khz, ? 60dbfs, note 6) fso/fsi = 44.1khz/48khz fso/fsi = 48khz/44.1khz fso/fsi = 48khz/192khz fso/fsi = 192khz/48khz worst case (fso/fsi = 48khz/32khz) dynamic range (input = 1khz, ? 60dbfs, a-weighted, note 6) fso/fsi = 44.1khz/48khz - - - - 132 - 136 136 136 136 - 140 - - - - - - db db db db db db ratio between input and output sample rate fso/fsi 1/6 6 - note 6. measured by audio precision system two cascade.
asahi kasei [ak4126] ms0544-e-00 2006/09 - 9 - filter characteristics (ta=25 c; avdd, dvdd=3.0 3.6v) parameter symbol min typ max units digital filter 0.985 fso/fsi 6.000 pb 0 0.4583fsi khz 0.905 fso/fsi < 0.985 pb 0 0.4167fsi khz 0.714 fso/fsi < 0.905 pb 0 0.3195fsi khz 0.656 fso/fsi < 0.714 pb 0 0.2852fsi khz 0.536 fso/fsi < 0.656 pb 0 0.2182fsi khz 0.492 fso/fsi < 0.536 pb 0 0.2177fsi khz 0.452 fso/fsi < 0.492 pb 0 0.1948fsi khz 0.357 fso/fsi < 0.452 pb 0 0.1458fsi khz 0.324 fso/fsi < 0.357 pb 0 0.1302fsi khz 0.246 fso/fsi < 0.324 pb 0 0.0917fsi khz 0.226 fso/fsi < 0.246 pb 0 0.0826fsi khz passband ? 0.01db 0.1667 fso/fsi < 0.226 pb 0 0.0583fsi khz 0.985 fso/fsi 6.000 sb 0.5417fsi khz 0.905 fso/fsi < 0.985 sb 0.5021fsi khz 0.714 fso/fsi < 0.905 sb 0.3965fsi khz 0.656 fso/fsi < 0.714 sb 0.3643fsi khz 0.536 fso/fsi < 0.656 sb 0.2974fsi khz 0.492 fso/fsi < 0.536 sb 0.2813fsi khz 0.452 fso/fsi < 0.492 sb 0.2604fsi khz 0.357 fso/fsi < 0.452 sb 0.2116fsi khz 0.324 fso/fsi < 0.357 sb 0.1969fsi khz 0.246 fso/fsi < 0.324 sb 0.1573fsi khz 0.226 fso/fsi < 0.246 sb 0.1471fsi khz stopband 0.1667 fso/fsi < 0.226 sb 0.1020fsi khz passband ripple pr 0.01 db 0.985 fso/fsi 6.000 sa 121.2 db 0.905 fso/fsi < 0.985 sa 121.4 db 0.714 fso/fsi < 0.905 sa 115.3 db 0.656 fso/fsi < 0.714 sa 116.9 db 0.536 fso/fsi < 0.656 sa 114.6 db 0.492 fso/fsi < 0.536 sa 100.2 db 0.452 fso/fsi < 0.492 sa 103.3 db 0.357 fso/fsi < 0.452 sa 102.0 db 0.324 fso/fsi < 0.357 sa 103.6 db 0.246 fso/fsi < 0.324 sa 104.0 db 0.226 fso/fsi < 0.246 sa 103.3 db stopband attenuation 0.1667 fso/fsi < 0.226 sa 73.2 db group delay (note 7) gd - 57 - 1/fs note 7. this value is the time from the rising edge of lrck after data is input to rising edge of lrck after data is output, when lrck for output data corresponds with lrck for input.
asahi kasei [ak4126] ms0544-e-00 2006/09 - 10 - dc characteristics (ta=25 c; avdd, dvdd=3.0 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage (iout= ? 400 a) low-level output voltage (iout=400 a) voh vol dvdd ? 0.4 - - - - 0.4 v v input leakage current iin - - 10 a power supplies power supply current normal operation (pdn pin = ?h?) fsi=fso=48khz: avdd=dvdd=3.3v fsi=fso=192khz: avdd=dvdd=3.3v avdd=dvdd=3.6v power down (pdn pin = ?l?) (note 8) avdd+dvdd 48 192 10 - - 250 100 ma ma ma a note 8. all digital input pins are held dvss. this value is measured after the internal sram is initialized by inputting ?0? data to sdti1, sdti2, and sdti3 during (ilrck x 100) cycles.
asahi kasei [ak4126] ms0544-e-00 2006/09 - 11 - switching characteristics (ta=25 c; avdd, dvdd=3.0 3.6v; c l =20pf) parameter symbol min typ max units lrck for input data (ilrck) frequency duty cycle fs duty 8 48 50 192 52 khz % lrck for output data (olrck) frequency duty cycle fs duty 8 48 50 192 52 khz % audio interface timing input port ibick period ibick pulse width low pulse width high ilrck edge to ibick ? ? (note 9) ibick ? ? to ilrck edge (note 9) sdti hold time from ibick ? ? sdti setup time to ibick ? ? tbck tbckl tbckh tlrb tblr tsdh tsds 1/64fs 27 27 15 15 15 15 ns ns ns ns ns ns ns output port obick period obick pulse width low pulse width high olrck edge to obick ? ? (note 9) obick ? ? to olrck edge (note 9) olrck to sdto (msb) (except i 2 s mode) obick ? ? to sdto tbck tbckl tbckh tlrb tblr tlrs tbsd 1/64fs 27 27 20 20 20 20 ns ns ns ns ns ns ns reset timing pdn pulse width (note 10) tpd 150 ns note 9. bick rising edge must not occur at the same time as lrck edge. note 10. the ak4126 can be reset by bringing the pdn pin = ?l?.
asahi kasei [ak4126] ms0544-e-00 2006/09 - 12 - ? timing diagram 1/fs lrck vih vil tbck bick tbckh tbckl vih vil clock timing lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd tsds sdti vil tsdh vih audio interface timing note: bick shows ibick and obick. lrck shows ilrck and olrck. sdti shows sdti1, sdti2 and sdti2. sdto shows sdto1, sdto2 and sdto3. tpd pdn vil power down & reset timing
asahi kasei [ak4126] ms0544-e-00 2006/09 - 13 - operation overview ? system clock & audio interface format for input port the input port works in slave mode. the clocks supply ilrck and ibick externally. an internal system clock is created by the internal pll using ilrck (mode 0 2 of table 2) or ibick (mode 4, 5, 7of table 2). the pll2-0 pins and idif2-0 pins select the pll mode. the pll2-0 pins and idif2-0 pins should be controlled when pdn pin = ?l?. the idif2-0 pins select the audio interface format for the input port. the audio data is msb first, 2?s complement format. the sdti is latched on the rising edge of ibick. select the audio interface format when pdn pin = ?l?. the audio interface format of sdti1, sdti2 and sdti3 becomes the same setting. the maximum input frequency of ibick is 64fsi. mode idif2 idif1 idif0 sdti format ibick frequency 0 l l l 16bit, lsb justified 32fsi 1 l l h 20bit, lsb justified 40fsi 2 l h l 24/20bit, msb justified 48fsi 3 l h h 24/16bit, i 2 s compatible 48fsi or 32fsi 4 h l l 24bit, lsb justified 48fsi 5 h l h reserved 6 h h l reserved 7 h h h reserved table 1. input audio interface format (input port) mode pll2 pll1 pll0 ilrck freq ibick freq smute (note 14) 0 l l l 8k 96khz 1 l l h manual 2 l h l 8k 192khz 16k 192khz (note 11) depending on idif2-0 (note 12) semi-auto 3 l h h reserved 4 h l l 32fsi (note 13) 5 h l h 8k 192khz (note 12) 64fsi manual 6 h h l reserved 7 h h h 8k 192khz (note 12) 64fsi semi-auto note 11. pll lock rage is changed by the value of r and c connected filt pin. refer to ?pll loop filter?. note 12. the ibcik must be continuous except when the clocks are changed. note 13. ibcik = 32fsi is supported only 16bit lsb justified and i 2 s compatible. note 14. refer to ?soft mute operation? for manual mode and semi-auto mode. table 2. pll setting (input port)
asahi kasei [ak4126] ms0544-e-00 2006/09 - 14 - ilrck ibick(32fs) 0 110 2 3 9 1112131415 0 12 3 1 0 10 9 1112131415 sdti(i) don't care 1 0 15 14 13 210 15 14 13 12 12 don't care 15:msb, 0:lsb sdti(i) 15 14 13 76543 210 15 14 13 15 76543 210 ibick(64fs) 0 118 2 3 19 20 31 0 1 2 3 1 0 18 19 20 31 17 17 lch data rch data figure 2. mode 0 timing ilrck ibick(64fs) 0 1 224310 12 1 0 31 24 sdti(i) don't care 0 8 10 19:msb, 0:lsb lch data rch data 19 8 don't care 19 1 12 13 13 12 figure 3. mode 1 timing ilrck ibick(64fs) 0 1 2202124310 12 1 0 22 20 21 31 24 22 23 23 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 23 1 2 3 4 figure 4. mode 2 timing (24bit msb) ilrck ibick(64fs) 0 1 225 21 24 0 12 1 0 22 25 21 24 22 23 23 3 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 1 2 3 4 figure 5. mode 3 timing (24bit i 2 s)
asahi kasei [ak4126] ms0544-e-00 2006/09 - 15 - ilrck ibick(64fs) 0 1 224310 12 1 0 31 24 89 89 sdti(i) don't care 0 8 10 23:msb, 0:lsb lch data rch data 23 8 don't care 23 1 figure 6. mode 4 timing note: sdti shows sdti1, sdti2 and sdti3. ? system clock & audio interface format for output port the output port works in slave mode. the clocks supply olrck and obick externally. the odif1-0 pins and obit1-0 pins select the audio interface format for the output port. the audio data is msb first, 2?s complement format. the sdto is clocked out on the falling edge of obick. select the audio interface format when pdn pin = ?l?. the audio interface format of sdto1, sdto2 and sdto3 becomes the same setting. the maximum input frequency of obick is 64fso. mode odif1 odif0 sdto format 0 l l lsb justified 1 l h (reserved) 2 h l msb justified 3 h h i 2 s compatible table 3. output audio interface format 1 (output port) obick frequency mode obit1 obit0 sdto msb justified, i 2 s lsb justified 0 l l 16bit 32fso 1 l h 18bit 36fso 2 h l 20bit 40fso 3 h h 24bit 48fso 64fso table 4. output audio interface format 2 (output port) olrck obick(64fs) 0 1 lch data rch data 89 sdto(o) 15:msb, 0:lsb sdto(o) 17:msb, 0:lsb sdto(o) 19:msb, 0:lsb sdto(o) 23:msb, 0:lsb 1 0 12 13 14 11 10 16 17 15 20 21 22 29 23 31 30 10 9 8 11 15 14 2 1 0 10 9 8 11 15 14 2 1 0 17 16 10 9 8 11 15 14 2 1 0 17 16 19 18 10 9 8 11 15 14 2 1 0 17 16 19 18 21 20 23 22 12 13 14 11 8 9 10 16 17 15 20 21 22 29 23 31 30 0 1 2 10 9 2 11 15 14 0 1 8 2 8 15 14 11 0 1 17 16 10 9 2 8 15 14 9 0 1 17 16 19 18 11 10 2 8 15 11 10 9 0 1 17 16 19 18 21 20 23 22 14 figure 7. lsb timing
asahi kasei [ak4126] ms0544-e-00 2006/09 - 16 - olrck obick(64fs) 0 1 2 lch data rch data 34 sdto(o) sdto(o) sdto(o) sdto(o) 23:msb, 0:lsb 34 15:msb, 0:lsb 17:msb, 0:lsb 19:msb, 0:lsb 321 4 8765 0 10 9 21 20 23 22 321 4 65 0 17 16 19 18 321 4 15 14 0 17 16 15 14 13 12 2 1 0 321 4 8765 0 10 9 21 20 23 22 321 4 65 0 17 16 19 18 321 4 15 14 0 17 16 15 14 13 12 2 1 0 0 31 1 2 0 31 1 2 19 18 17 24 13 14 16 15 20 21 23 22 19 18 17 24 13 14 16 15 20 21 23 22 23 22 19 18 17 16 15 14 figure 8. msb timing olrck obick(64fs) 0 1 2 lch data rch data 34 sdto(o) sdto(o) sdto(o) sdto(o) 23:msb, 0:lsb 34 15:msb, 0:lsb 17:msb, 0:lsb 19:msb, 0:lsb 012 0 31 1 2 19 18 17 24 14 16 15 20 21 23 22 19 18 17 24 14 16 15 20 21 23 22 23 19 17 15 15 14 13 12 2 1 0 321 4 15 14 0 17 16 321 4 65 0 17 16 19 18 321 4 8765 0 10 9 21 20 23 22 15 14 13 12 2 1 0 321 4 15 14 0 17 16 321 4 65 0 17 16 19 18 321 4 8765 0 10 9 21 20 23 22 figure 9. i 2 s compatible timing note: sdto shows sdto1, sdto2 and sdto3. ? 4-channel mode the ak4126 has 4-channel mode to reduce power supply current when using four channels in six channels. when pm pin is set to ?h?, four channels (sdti1 ? sdto1 and sdti2 ? sdto2) in six channels work, and other 2 channels (sdti3 ? sdto3) are powered-down (sdto3 outputs ?l?.). pm pin mode l 6-channel mode h 4-channel mode table 5. channel mode setting
asahi kasei [ak4126] ms0544-e-00 2006/09 - 17 - ? soft mute operation 1. manual mode the soft mute operation is performed in the digital domain of the src output. the soft mute can be controlled by smute pin. when smute pin goes ?h?, all the src output data are attenuated by ? during 1024 olrck cycles (@ smt1 pin = ?l? and smt0 pin = ?l?). when the smute pin goes ?l? the mute is cancelled and the output attenuation gradually changes to 0db during 1024 olrck cycles (@ smt1 pin = ?l? and smt0 pin = ?l?). if the soft mute is cancelled before mute state after starting of the operation, the attenuation is discontinued and returned to 0db by the same cycles. the soft mute is effective for changing the signal source. soft mute cycle is selected by smt1-0 pins. smt1-0 pins must not be changed during soft mute transition. smt1pin smt0 pin period fso=48khz fso=96khz fso=192khz l l 1024/fso 21.3ms 10.7ms 5.3ms l h 2048/fso 42.7ms 21.3ms 10.7ms h l 4096/fso 85.3ms 42.7ms 21.3ms h h 8192/fso 170.7ms 85.3ms 42.7ms table 6. soft mute cycle setting smute a ttenuation 0db - (1) (2) sdto (1) note: sdto shows sdto1, sdto2 and sdto3. (1) the soft mute cycle is selected by smt1-0 pins. (see table 6) the output data is attenuated by ? during the soft mute cycle. (2) if the soft mute is cancelled before attenuating to ? after starting the operation, the attenuation is discontinued and returned to 0db by the same number of clock cycles. figure 10. soft mute function (manual mode)
asahi kasei [ak4126] ms0544-e-00 2006/09 - 18 - 2. semi-auto mode the soft mute is cancelled automatically by the setting of pll2-0 pins (refer to table 2), after the ak4126 detects the rising edge (pdn pin = ?l? ?h?) and the mute is continued duri ng 4410/fso=100ms@fso=44.1khz. after pdn pin = ?l? ?h? and when smute pin is ?h?, the mute is not cancelled. pdn pin a ttenuation 0db - sdto 4410/fso (1) smute pin don?t care ?l? ?l? note: sdto shows sdto1, sdto2 and sdto3. (1) the output data is attenuated by ? during the soft mute cycle (see table 6) figure 11. soft mute function (semi-auto mode) ? dither the ak4126 includes the dither circuit. the dither circuit adds the dither to the lsb of all the output data set with the obit1-0 pins by dither pin = ?h?. ? de-emphasis filter the ak4126 includes a digital de-emphasis filter (tc = 50/15 s) via an iir filter. this filter corresponds to three frequencies (32khz, 44.1khz and 48khz). this setting is done via dem1-0 pins (see table 7), and it is applied to all input data. dem1pin dem0 pin mode l l 44.1khz l h off h l 48khz h h 32khz table 7. de-emphasis filter setting
asahi kasei [ak4126] ms0544-e-00 2006/09 - 19 - ? system reset bringing the pdn pin = ?l? sets the ak 4126 power-down mode and initializes th e digital filter. the ak4126 should be reset once by bringing pdn pin = ?l? upon power-up. when p dn pin = ?l?, the sdto output is ?l?. the sdto valid time is 100ms. until then, the sdto outputs ?l?. (sdt o shows sdto1, sdto2 and sdto3. sdti shows sdti1, sdti2 and sdti3.) case 1 external clocks (input port) sdti don?t care sdto (internal state) power-down normal operation pll lock & fs detection < 100ms normal data input clocks 1 external clocks (output port) don?t care don?t care pdn power-down don?t care don?t care don?t care ?0? data normal operation pll lock & fs detection < 100ms normal data pd input data 1 output clocks 1 input clocks 2 input data 2 output clocks 2 ?0? data ?0? data unlock figure 12. system reset case 2 external clocks (input port) sdti sdto (internal state) power-down normal operation pll lock & fs detection < 100ms normal data (no clock) external clocks (output port) pdn power-down don?t care don?t care don?t care ?0? data pll unlock input clocks input data output clocks ?0? data (don?t care) (don?t care) unlock figure 13. system reset 2
asahi kasei [ak4126] ms0544-e-00 2006/09 - 20 - ? internal reset function for clock change the change of the clock supplied to the ak4126 is shown in figure 14. sdto shows sdto1, sdto2 and sdto3. pll lock & fs detection power-down external clocks (input port or output port) clocks 1 sdto (internal state) normal operation normal operation clocks 2 don?t care < 100ms smute (note2, recommended) (1) a tt.level 0db - db normal data normal data (1) pdn pin note1 (1) soft mute cycle. (see table 6) e.g. smt1 pin = ?l?, smt0 pin = ?l?, fso = 48khz soft mute cycle: 1024/fso = 21.3ms note 1. the data on sdto may cause a clicking noise. to prevent this, set sdti to ?0? from gd before pdn pin goes ?l?, which will cause the data on sdto to remain ?0?. note 2. smute can also be used to remove the unknown data. figure 14. sequence of changing clocks ? unlock pin the unlock pin outputs ?l? when the internal pll is locked. when the internal pll is unlocked, the unlock pin outputs ?h?. when pdn pin = ?l?, the unlock pin outputs ?h?.
asahi kasei [ak4126] ms0544-e-00 2006/09 - 21 - ? pll loop filter the c1 and r should be connected in series and attached between filt pin and avss in parallel with c2. (see figure 15, table 8 and table 9) please be careful the noise onto the filt pin. when using ibick, the value of an external element doesn't depend on the ibick input frequency. ak4126 c1 r filt a vss c2 figure 15. pll loop filter 1. when using ilrck pll2 pll1 pll0 ilrck r [ ? ] c1 [ f] c2 [nf] l l l 8k 96khz 1.8k 5% 0.68 30% 0.68 30% 8k 192khz 1k 5% 1.0 30% 2.2 30% l l h 16k 192khz 1.5k 5% 0.68 30% 0.68 30% 8k 192khz 1k 5% 1.0 30% 2.2 30% l h l 16k 192khz 1.5k 5% 0.68 30% 0.68 30% table 8. pll loop filter (ilrck mode) - note. smaller value can be selected for the capacitors (c1, c2) in case of ilrck range from 16khz to 192khz. - note. tolerance of r, c1, and c2 includes the temperature characteristics. 2. when using ibick pll2 pll1 pll0 ilrck r [ ? ] c1 [ f] c2 [nf] h x x 8k 192khz 470 5% 0.22 30% 1.0 30% table 9. pll loop filter (ibick mode, ?x?: don?t care) - note. the ibcik must be continuous except when the clocks are changed. - note. ibcik = 32fsi is supported only 16bit lsb justified and i 2 s compatible. - note. tolerance of r, c1, and c2 includes the temperature characteristics.
asahi kasei [ak4126] ms0544-e-00 2006/09 - 22 - system design figure 16 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ? input port: slave mode, ibick lock mode (64fsi), 24 bit msb justified ? output port: slave mode, 24 bit msb justified ? dither = off, de-emphasis = off, pm = 6ch mode nc 1 2 3 4 5 6 7 8 9 10 11 test0 ilrck ibick dvdd dvss tst0 sdti1 sdti2 sdti3 idif0 top view nc 64 63 62 tst11 avss 61 60 58 57 59 55 54 56 53 filt avdd nc tst10 tst9 pll0 pll1 pll2 dvss 12 idif1 13 idif2 14 tst1 15 tst2 16 nc 52 dvdd 51 tst8 50 tst7 49 nc tst3 17 tst4 18 unlock 19 dvdd 20 dvss 21 smute 22 dither 23 pdn 24 smt0 25 smt1 26 dem0 27 dem1 28 pm 29 obit0 30 obit1 31 tst5 32 44 43 42 41 40 39 38 37 36 35 34 33 dvdd dvss tst6 sdto1 sdto2 sdto3 odif0 odif1 test3 test2 test1 nc 45 obick 46 olrck 47 test4 48 nc 470 ? 1n dsp1 up 3.3v c2 c1 c1 c1 + c1: 0.1 c2: 10 + 0.22 dsp2 c1 c1 c2 + c2 fsi 64fsi fso 64fso notes: - all digital input pins should be not left floating. - avss and dvss must be connected to the same ground plane. figure 16. typical connection diagram
asahi kasei [ak4126] ms0544-e-00 2006/09 - 23 - 1. grounding and power supply decoupling the ak4126 requires careful attention to power supply and grounding arrangements. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical . avss and dvss must be connected to the same ground plane. decoupling capacitors should be as near to the ak4126 as possible, with the small value ceramic capacitor being the nearest. 2. jitter tolerance figure 17 shows the jitter tolerance to ilrck and ibick for ak4126. the jitter frequency and the jitter amplitude shown in figure 17 define the jitter quantity. when the jitter amplitude is 0.01uipp or less, the ak4126 operate normally regardless of the jitter frequency. (1) normal operation (2) there is a possibility that the distortion degrades. (it may degrade up to about ? 50db.) (3) there is a possibility that the output data is lost. note: - when pll2-0 = ?l/l/l?, ?l/l/h?, ?l/h/l?, the jitter amplitude is for ilrck and 1ui (unit interval) is one cycle of ilrck. when fsi = 48khz, 1ui is 1/48khz = 20.8 s. - when pll2-0 = ?h/*/*? (*: don?t care), the jitter amplitude is for ibick and 1ui (unit interval) is one cycle of ibick. when fsi = 48khz, 1ui is 1/(64 x 48khz) = 326ns. figure 17. jitter tolerance ak4125 jitter tolerance 0.00 0.01 0.10 1.00 10.00 1 10 100 1000 10000 jitter frequency [hz] amplitude [uipp] (3) (2) (1) ak4126 jitter tolerance
asahi kasei [ak4126] ms0544-e-00 2006/09 - 24 - tracking to the input sampling frequency when the ilrck is generated by an external pll, it may take a time to settle after changing the input sampling frequency because the response of an external pll to the frequency change is slow. ak4126 operates normally up to 23%/sec speed and the output data becomes incorrect at the speed of the frequency change over 23%/sec. 3. digital filter response example table 10 shows the examples of digital filter response performed by the ak4126. ratio fso/fsi [khz] passband [khz] stopband [khz] stopband attenuation [db] gain [db] 4.000 192/48.0 22.000 26.000 ? 121.2 ? 0.01@ 20k 1.000 48.0/48.0 22.000 26.000 ? 121.2 ? 0.01@ 20k 0.919 44.1/48.0 20.000 24.100 ? 121.4 ? 0.01@ 20k 0.725 32.0/44.1 14.088 17.487 ? 115.3 ? 0.01@ 14.5k 0.667 32.0/48.0 13.688 17.488 ? 116.9 ? 0.19@ 14.5k 0.544 48.0/88.2 19.250 26.232 ? 114.6 ? 0.03@ 20k 0.500 48.0/96.0 20.900 27.000 ? 100.2 ? 0.01@ 20k 0.500 44.1/88.2 19.202 24.806 ? 100.2 ? 0.08@ 20k 0.459 44.1/96.0 18.700 25.000 ? 103.3 ? 0.23@ 20k 0.363 32.0/88.2 12.863 18.665 ? 102.0 ? 0.75@ 14.5k 0.333 32.0/96.0 12.500 18.900 ? 103.6 ? 1.07@ 14.5k 0.250 48.0/192.0 17.600 30.200 ? 104.0 ? 0.18@ 20k 0.250 44.1/176.4 16.170 27.746 ? 104.0 ? 1.34@ 20k 0.230 44.1/192.0 15.860 28.240 ? 103.3 ? 1.40@ 20k 0.167 32.0/192.0 11.200 19.600 ? 73.2 ? 2.97@ 14.5k 0.181 32.0/176.4 10.278 17.987 ? 73.2 ? 7.88@ 14.5k 0.167 8/48.0 2.800 4.900 ? 73.2 ? 2.97@ 3.625k 0.181 8/44.1 2.5695 4.4968 ? 73.2 ? 7.88@ 3.625k table 10. digital filter example
asahi kasei [ak4126] ms0544-e-00 2006/09 - 25 - package ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate 12.00.3 0.210.05 0.170.05 12.00.3 1 16 17 32 33 48 49 64 0.10 0.5 1.70max 0.100.10 0 ~10 0.450.2 10.0 64pin lqfp(unit:mm) 1.40 0.10 m 1.0
asahi kasei [ak4126] ms0544-e-00 2006/09 - 26 - marking 1 akm AK4126VQ xxxxxxx xxxxxxx: date code identifier revision history date (yy/mm/dd) revision reason page contents 06/09/20 00 first edition
asahi kasei [ak4126] ms0544-e-00 2006/09 - 27 - important notice ? these products and their specifications are subjec t to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any pat ent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all cl aims arising from the use of said product in the absence of such notification.

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